LXR qemu/cpu-common.h

   1#ifndef CPU_COMMON_H
   2#define CPU_COMMON_H 1
   3
   4/* CPU interfaces that are target independent.  */
   5
   6#ifdef TARGET_PHYS_ADDR_BITS
   7#include "targphys.h"
   8#endif
   9
  10#ifndef NEED_CPU_H
  11#include "poison.h"
  12#endif
  13
  14#include "bswap.h"
  15#include "qemu-queue.h"
  16
  17#if !defined(CONFIG_USER_ONLY)
  18
  19enum device_endian {
  20    DEVICE_NATIVE_ENDIAN,
  21    DEVICE_BIG_ENDIAN,
  22    DEVICE_LITTLE_ENDIAN,
  23};
  24
  25/* address in the RAM (different from a physical address) */
  26#if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
  27typedef uint64_t ram_addr_t;
  28#  define RAM_ADDR_MAX UINT64_MAX
  29#  define RAM_ADDR_FMT "%" PRIx64
  30#else
  31typedef uintptr_t ram_addr_t;
  32#  define RAM_ADDR_MAX UINTPTR_MAX
  33#  define RAM_ADDR_FMT "%" PRIxPTR
  34#endif
  35
  36/* memory API */
  37
  38typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
  39typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
  40
  41void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  42/* This should only be used for ram local to a device.  */
  43void *qemu_get_ram_ptr(ram_addr_t addr);
  44void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
  45/* Same but slower, to use for migration, where the order of
  46 * RAMBlocks must not change. */
  47void *qemu_safe_ram_ptr(ram_addr_t addr);
  48void qemu_put_ram_ptr(void *addr);
  49/* This should not be used by devices.  */
  50int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  51ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
  52void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
  53
  54void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
  55                            int len, int is_write);
  56static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  57                                            void *buf, int len)
  58{
  59    cpu_physical_memory_rw(addr, buf, len, 0);
  60}
  61static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  62                                             const void *buf, int len)
  63{
  64    cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  65}
  66void *cpu_physical_memory_map(target_phys_addr_t addr,
  67                              target_phys_addr_t *plen,
  68                              int is_write);
  69void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
  70                               int is_write, target_phys_addr_t access_len);
  71void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
  72void cpu_unregister_map_client(void *cookie);
  73
  74/* Coalesced MMIO regions are areas where write operations can be reordered.
  75 * This usually implies that write operations are side-effect free.  This allows
  76 * batching which can make a major impact on performance when using
  77 * virtualization.
  78 */
  79void qemu_flush_coalesced_mmio_buffer(void);
  80
  81uint32_t ldub_phys(target_phys_addr_t addr);
  82uint32_t lduw_le_phys(target_phys_addr_t addr);
  83uint32_t lduw_be_phys(target_phys_addr_t addr);
  84uint32_t ldl_le_phys(target_phys_addr_t addr);
  85uint32_t ldl_be_phys(target_phys_addr_t addr);
  86uint64_t ldq_le_phys(target_phys_addr_t addr);
  87uint64_t ldq_be_phys(target_phys_addr_t addr);
  88void stb_phys(target_phys_addr_t addr, uint32_t val);
  89void stw_le_phys(target_phys_addr_t addr, uint32_t val);
  90void stw_be_phys(target_phys_addr_t addr, uint32_t val);
  91void stl_le_phys(target_phys_addr_t addr, uint32_t val);
  92void stl_be_phys(target_phys_addr_t addr, uint32_t val);
  93void stq_le_phys(target_phys_addr_t addr, uint64_t val);
  94void stq_be_phys(target_phys_addr_t addr, uint64_t val);
  95
  96#ifdef NEED_CPU_H
  97uint32_t lduw_phys(target_phys_addr_t addr);
  98uint32_t ldl_phys(target_phys_addr_t addr);
  99uint64_t ldq_phys(target_phys_addr_t addr);
 100void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 101void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 102void stw_phys(target_phys_addr_t addr, uint32_t val);
 103void stl_phys(target_phys_addr_t addr, uint32_t val);
 104void stq_phys(target_phys_addr_t addr, uint64_t val);
 105#endif
 106
 107void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 108                                   const uint8_t *buf, int len);
 109
 110extern struct MemoryRegion io_mem_ram;
 111extern struct MemoryRegion io_mem_rom;
 112extern struct MemoryRegion io_mem_unassigned;
 113extern struct MemoryRegion io_mem_notdirty;
 114
 115#endif
 116
 117#endif /* !CPU_COMMON_H */
 118