1
2#include "config.h"
3#include "dis-asm.h"
4#include "elf.h"
5#include <errno.h>
6
7#include "cpu.h"
8#include "disas.h"
9
10
11struct syminfo *syminfos = NULL;
12
13
14
15int
16buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
17 struct disassemble_info *info)
18{
19 if (memaddr < info->buffer_vma
20 || memaddr + length > info->buffer_vma + info->buffer_length)
21
22 return EIO;
23 memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
24 return 0;
25}
26
27
28
29static int
30target_read_memory (bfd_vma memaddr,
31 bfd_byte *myaddr,
32 int length,
33 struct disassemble_info *info)
34{
35 cpu_memory_rw_debug(cpu_single_env, memaddr, myaddr, length, 0);
36 return 0;
37}
38
39
40
41void
42perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
43{
44 if (status != EIO)
45
46 (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
47 else
48
49
50 (*info->fprintf_func) (info->stream,
51 "Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
52}
53
54
55
56
57
58
59
60
61void
62generic_print_address (bfd_vma addr, struct disassemble_info *info)
63{
64 (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
65}
66
67
68static void
69generic_print_target_address(bfd_vma addr, struct disassemble_info *info)
70{
71 uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS);
72 generic_print_address(addr & mask, info);
73}
74
75
76static void
77generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
78{
79 uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8));
80 generic_print_address(addr & mask, info);
81}
82
83
84
85int
86generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
87{
88 return 1;
89}
90
91bfd_vma bfd_getl64 (const bfd_byte *addr)
92{
93 unsigned long long v;
94
95 v = (unsigned long long) addr[0];
96 v |= (unsigned long long) addr[1] << 8;
97 v |= (unsigned long long) addr[2] << 16;
98 v |= (unsigned long long) addr[3] << 24;
99 v |= (unsigned long long) addr[4] << 32;
100 v |= (unsigned long long) addr[5] << 40;
101 v |= (unsigned long long) addr[6] << 48;
102 v |= (unsigned long long) addr[7] << 56;
103 return (bfd_vma) v;
104}
105
106bfd_vma bfd_getl32 (const bfd_byte *addr)
107{
108 unsigned long v;
109
110 v = (unsigned long) addr[0];
111 v |= (unsigned long) addr[1] << 8;
112 v |= (unsigned long) addr[2] << 16;
113 v |= (unsigned long) addr[3] << 24;
114 return (bfd_vma) v;
115}
116
117bfd_vma bfd_getb32 (const bfd_byte *addr)
118{
119 unsigned long v;
120
121 v = (unsigned long) addr[0] << 24;
122 v |= (unsigned long) addr[1] << 16;
123 v |= (unsigned long) addr[2] << 8;
124 v |= (unsigned long) addr[3];
125 return (bfd_vma) v;
126}
127
128bfd_vma bfd_getl16 (const bfd_byte *addr)
129{
130 unsigned long v;
131
132 v = (unsigned long) addr[0];
133 v |= (unsigned long) addr[1] << 8;
134 return (bfd_vma) v;
135}
136
137bfd_vma bfd_getb16 (const bfd_byte *addr)
138{
139 unsigned long v;
140
141 v = (unsigned long) addr[0] << 24;
142 v |= (unsigned long) addr[1] << 16;
143 return (bfd_vma) v;
144}
145
146#ifdef TARGET_ARM
147static int
148print_insn_thumb1(bfd_vma pc, disassemble_info *info)
149{
150 return print_insn_arm(pc | 1, info);
151}
152#endif
153
154
155
156
157
158
159
160
161void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
162{
163 target_ulong pc;
164 int count;
165 struct disassemble_info disasm_info;
166 int (*print_insn)(bfd_vma pc, disassemble_info *info);
167
168 INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
169
170 disasm_info.read_memory_func = target_read_memory;
171 disasm_info.buffer_vma = code;
172 disasm_info.buffer_length = size;
173 disasm_info.print_address_func = generic_print_target_address;
174
175#ifdef TARGET_WORDS_BIGENDIAN
176 disasm_info.endian = BFD_ENDIAN_BIG;
177#else
178 disasm_info.endian = BFD_ENDIAN_LITTLE;
179#endif
180#if defined(TARGET_I386)
181 if (flags == 2)
182 disasm_info.mach = bfd_mach_x86_64;
183 else if (flags == 1)
184 disasm_info.mach = bfd_mach_i386_i8086;
185 else
186 disasm_info.mach = bfd_mach_i386_i386;
187 print_insn = print_insn_i386;
188#elif defined(TARGET_ARM)
189 if (flags & 1) {
190 print_insn = print_insn_thumb1;
191 } else {
192 print_insn = print_insn_arm;
193 }
194 if (flags & 2) {
195#ifdef TARGET_WORDS_BIGENDIAN
196 disasm_info.endian = BFD_ENDIAN_LITTLE;
197#else
198 disasm_info.endian = BFD_ENDIAN_BIG;
199#endif
200 }
201#elif defined(TARGET_SPARC)
202 print_insn = print_insn_sparc;
203#ifdef TARGET_SPARC64
204 disasm_info.mach = bfd_mach_sparc_v9b;
205#endif
206#elif defined(TARGET_PPC)
207 if (flags >> 16)
208 disasm_info.endian = BFD_ENDIAN_LITTLE;
209 if (flags & 0xFFFF) {
210
211 disasm_info.mach = flags & 0xFFFF;
212 } else {
213#ifdef TARGET_PPC64
214 disasm_info.mach = bfd_mach_ppc64;
215#else
216 disasm_info.mach = bfd_mach_ppc;
217#endif
218 }
219 print_insn = print_insn_ppc;
220#elif defined(TARGET_M68K)
221 print_insn = print_insn_m68k;
222#elif defined(TARGET_MIPS)
223#ifdef TARGET_WORDS_BIGENDIAN
224 print_insn = print_insn_big_mips;
225#else
226 print_insn = print_insn_little_mips;
227#endif
228#elif defined(TARGET_SH4)
229 disasm_info.mach = bfd_mach_sh4;
230 print_insn = print_insn_sh;
231#elif defined(TARGET_ALPHA)
232 disasm_info.mach = bfd_mach_alpha_ev6;
233 print_insn = print_insn_alpha;
234#elif defined(TARGET_CRIS)
235 if (flags != 32) {
236 disasm_info.mach = bfd_mach_cris_v0_v10;
237 print_insn = print_insn_crisv10;
238 } else {
239 disasm_info.mach = bfd_mach_cris_v32;
240 print_insn = print_insn_crisv32;
241 }
242#elif defined(TARGET_S390X)
243 disasm_info.mach = bfd_mach_s390_64;
244 print_insn = print_insn_s390;
245#elif defined(TARGET_MICROBLAZE)
246 disasm_info.mach = bfd_arch_microblaze;
247 print_insn = print_insn_microblaze;
248#elif defined(TARGET_LM32)
249 disasm_info.mach = bfd_mach_lm32;
250 print_insn = print_insn_lm32;
251#else
252 fprintf(out, "0x" TARGET_FMT_lx
253 ": Asm output not supported on this arch\n", code);
254 return;
255#endif
256
257 for (pc = code; size > 0; pc += count, size -= count) {
258 fprintf(out, "0x" TARGET_FMT_lx ": ", pc);
259 count = print_insn(pc, &disasm_info);
260#if 0
261 {
262 int i;
263 uint8_t b;
264 fprintf(out, " {");
265 for(i = 0; i < count; i++) {
266 target_read_memory(pc + i, &b, 1, &disasm_info);
267 fprintf(out, " %02x", b);
268 }
269 fprintf(out, " }");
270 }
271#endif
272 fprintf(out, "\n");
273 if (count < 0)
274 break;
275 if (size < count) {
276 fprintf(out,
277 "Disassembler disagrees with translator over instruction "
278 "decoding\n"
279 "Please report this to qemu-devel@nongnu.org\n");
280 break;
281 }
282 }
283}
284
285
286void disas(FILE *out, void *code, unsigned long size)
287{
288 uintptr_t pc;
289 int count;
290 struct disassemble_info disasm_info;
291 int (*print_insn)(bfd_vma pc, disassemble_info *info);
292
293 INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
294 disasm_info.print_address_func = generic_print_host_address;
295
296 disasm_info.buffer = code;
297 disasm_info.buffer_vma = (uintptr_t)code;
298 disasm_info.buffer_length = size;
299
300#ifdef HOST_WORDS_BIGENDIAN
301 disasm_info.endian = BFD_ENDIAN_BIG;
302#else
303 disasm_info.endian = BFD_ENDIAN_LITTLE;
304#endif
305#if defined(CONFIG_TCG_INTERPRETER)
306 print_insn = print_insn_tci;
307#elif defined(__i386__)
308 disasm_info.mach = bfd_mach_i386_i386;
309 print_insn = print_insn_i386;
310#elif defined(__x86_64__)
311 disasm_info.mach = bfd_mach_x86_64;
312 print_insn = print_insn_i386;
313#elif defined(_ARCH_PPC)
314 print_insn = print_insn_ppc;
315#elif defined(__alpha__)
316 print_insn = print_insn_alpha;
317#elif defined(__sparc__)
318 print_insn = print_insn_sparc;
319#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
320 disasm_info.mach = bfd_mach_sparc_v9b;
321#endif
322#elif defined(__arm__)
323 print_insn = print_insn_arm;
324#elif defined(__MIPSEB__)
325 print_insn = print_insn_big_mips;
326#elif defined(__MIPSEL__)
327 print_insn = print_insn_little_mips;
328#elif defined(__m68k__)
329 print_insn = print_insn_m68k;
330#elif defined(__s390__)
331 print_insn = print_insn_s390;
332#elif defined(__hppa__)
333 print_insn = print_insn_hppa;
334#elif defined(__ia64__)
335 print_insn = print_insn_ia64;
336#else
337 fprintf(out, "0x%lx: Asm output not supported on this arch\n",
338 (long) code);
339 return;
340#endif
341 for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
342 fprintf(out, "0x%08" PRIxPTR ": ", pc);
343 count = print_insn(pc, &disasm_info);
344 fprintf(out, "\n");
345 if (count < 0)
346 break;
347 }
348}
349
350
351const char *lookup_symbol(target_ulong orig_addr)
352{
353 const char *symbol = "";
354 struct syminfo *s;
355
356 for (s = syminfos; s; s = s->next) {
357 symbol = s->lookup_symbol(s, orig_addr);
358 if (symbol[0] != '\0') {
359 break;
360 }
361 }
362
363 return symbol;
364}
365
366#if !defined(CONFIG_USER_ONLY)
367
368#include "monitor.h"
369
370static int monitor_disas_is_physical;
371static CPUArchState *monitor_disas_env;
372
373static int
374monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
375 struct disassemble_info *info)
376{
377 if (monitor_disas_is_physical) {
378 cpu_physical_memory_read(memaddr, myaddr, length);
379 } else {
380 cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, 0);
381 }
382 return 0;
383}
384
385static int GCC_FMT_ATTR(2, 3)
386monitor_fprintf(FILE *stream, const char *fmt, ...)
387{
388 va_list ap;
389 va_start(ap, fmt);
390 monitor_vprintf((Monitor *)stream, fmt, ap);
391 va_end(ap);
392 return 0;
393}
394
395void monitor_disas(Monitor *mon, CPUArchState *env,
396 target_ulong pc, int nb_insn, int is_physical, int flags)
397{
398 int count, i;
399 struct disassemble_info disasm_info;
400 int (*print_insn)(bfd_vma pc, disassemble_info *info);
401
402 INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf);
403
404 monitor_disas_env = env;
405 monitor_disas_is_physical = is_physical;
406 disasm_info.read_memory_func = monitor_read_memory;
407 disasm_info.print_address_func = generic_print_target_address;
408
409 disasm_info.buffer_vma = pc;
410
411#ifdef TARGET_WORDS_BIGENDIAN
412 disasm_info.endian = BFD_ENDIAN_BIG;
413#else
414 disasm_info.endian = BFD_ENDIAN_LITTLE;
415#endif
416#if defined(TARGET_I386)
417 if (flags == 2)
418 disasm_info.mach = bfd_mach_x86_64;
419 else if (flags == 1)
420 disasm_info.mach = bfd_mach_i386_i8086;
421 else
422 disasm_info.mach = bfd_mach_i386_i386;
423 print_insn = print_insn_i386;
424#elif defined(TARGET_ARM)
425 print_insn = print_insn_arm;
426#elif defined(TARGET_ALPHA)
427 print_insn = print_insn_alpha;
428#elif defined(TARGET_SPARC)
429 print_insn = print_insn_sparc;
430#ifdef TARGET_SPARC64
431 disasm_info.mach = bfd_mach_sparc_v9b;
432#endif
433#elif defined(TARGET_PPC)
434#ifdef TARGET_PPC64
435 disasm_info.mach = bfd_mach_ppc64;
436#else
437 disasm_info.mach = bfd_mach_ppc;
438#endif
439 print_insn = print_insn_ppc;
440#elif defined(TARGET_M68K)
441 print_insn = print_insn_m68k;
442#elif defined(TARGET_MIPS)
443#ifdef TARGET_WORDS_BIGENDIAN
444 print_insn = print_insn_big_mips;
445#else
446 print_insn = print_insn_little_mips;
447#endif
448#elif defined(TARGET_SH4)
449 disasm_info.mach = bfd_mach_sh4;
450 print_insn = print_insn_sh;
451#elif defined(TARGET_S390X)
452 disasm_info.mach = bfd_mach_s390_64;
453 print_insn = print_insn_s390;
454#elif defined(TARGET_LM32)
455 disasm_info.mach = bfd_mach_lm32;
456 print_insn = print_insn_lm32;
457#else
458 monitor_printf(mon, "0x" TARGET_FMT_lx
459 ": Asm output not supported on this arch\n", pc);
460 return;
461#endif
462
463 for(i = 0; i < nb_insn; i++) {
464 monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
465 count = print_insn(pc, &disasm_info);
466 monitor_printf(mon, "\n");
467 if (count < 0)
468 break;
469 pc += count;
470 }
471}
472#endif
473