1#ifndef __QEMU_BARRIER_H
2#define __QEMU_BARRIER_H 1
3
4
5#define barrier() asm volatile("" ::: "memory")
6
7#if defined(__i386__)
8
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13
14
15#define smp_wmb() barrier()
16#define smp_rmb() barrier()
17
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21
22#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 4
23#define smp_mb() __sync_synchronize()
24#else
25#define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
26#endif
27
28#elif defined(__x86_64__)
29
30#define smp_wmb() barrier()
31#define smp_rmb() barrier()
32#define smp_mb() asm volatile("mfence" ::: "memory")
33
34#elif defined(_ARCH_PPC)
35
36
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38
39
40
41#define smp_wmb() asm volatile("eieio" ::: "memory")
42
43#if defined(__powerpc64__)
44#define smp_rmb() asm volatile("lwsync" ::: "memory")
45#else
46#define smp_rmb() asm volatile("sync" ::: "memory")
47#endif
48
49#define smp_mb() asm volatile("sync" ::: "memory")
50
51#else
52
53
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56
57
58
59#define smp_wmb() __sync_synchronize()
60#define smp_mb() __sync_synchronize()
61#define smp_rmb() __sync_synchronize()
62
63#endif
64
65#endif
66