1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <stdio.h>
19#include "dis-asm.h"
20
21#define DEFINE_TABLE
22
23typedef enum
24 {
25 HEX_0,
26 HEX_1,
27 HEX_2,
28 HEX_3,
29 HEX_4,
30 HEX_5,
31 HEX_6,
32 HEX_7,
33 HEX_8,
34 HEX_9,
35 HEX_A,
36 HEX_B,
37 HEX_C,
38 HEX_D,
39 HEX_E,
40 HEX_F,
41 HEX_XX00,
42 HEX_00YY,
43 REG_N,
44 REG_N_D,
45 REG_N_B01,
46 REG_M,
47 SDT_REG_N,
48 REG_NM,
49 REG_B,
50 BRANCH_12,
51 BRANCH_8,
52 IMM0_4,
53 IMM0_4BY2,
54 IMM0_4BY4,
55 IMM1_4,
56 IMM1_4BY2,
57 IMM1_4BY4,
58 PCRELIMM_8BY2,
59 PCRELIMM_8BY4,
60 IMM0_8,
61 IMM0_8BY2,
62 IMM0_8BY4,
63 IMM1_8,
64 IMM1_8BY2,
65 IMM1_8BY4,
66 PPI,
67 NOPX,
68 NOPY,
69 MOVX,
70 MOVY,
71 MOVX_NOPY,
72 MOVY_NOPX,
73 PSH,
74 PMUL,
75 PPI3,
76 PPI3NC,
77 PDC,
78 PPIC,
79 REPEAT,
80 IMM0_3c,
81 IMM0_3s,
82 IMM0_3Uc,
83 IMM0_3Us,
84 IMM0_20_4,
85 IMM0_20,
86 IMM0_20BY8,
87 DISP0_12,
88 DISP0_12BY2,
89 DISP0_12BY4,
90 DISP0_12BY8,
91 DISP1_12,
92 DISP1_12BY2,
93 DISP1_12BY4,
94 DISP1_12BY8
95 }
96sh_nibble_type;
97
98typedef enum
99 {
100 A_END,
101 A_BDISP12,
102 A_BDISP8,
103 A_DEC_M,
104 A_DEC_N,
105 A_DISP_GBR,
106 A_PC,
107 A_DISP_PC,
108 A_DISP_PC_ABS,
109 A_DISP_REG_M,
110 A_DISP_REG_N,
111 A_GBR,
112 A_IMM,
113 A_INC_M,
114 A_INC_N,
115 A_IND_M,
116 A_IND_N,
117 A_IND_R0_REG_M,
118 A_IND_R0_REG_N,
119 A_MACH,
120 A_MACL,
121 A_PR,
122 A_R0,
123 A_R0_GBR,
124 A_REG_M,
125 A_REG_N,
126 A_REG_B,
127 A_SR,
128 A_VBR,
129 A_TBR,
130 A_DISP_TBR,
131 A_DISP2_TBR,
132 A_DEC_R15,
133 A_INC_R15,
134 A_MOD,
135 A_RE,
136 A_RS,
137 A_DSR,
138 DSP_REG_M,
139 DSP_REG_N,
140 DSP_REG_X,
141 DSP_REG_Y,
142 DSP_REG_E,
143 DSP_REG_F,
144 DSP_REG_G,
145 DSP_REG_A_M,
146 DSP_REG_AX,
147 DSP_REG_XY,
148 DSP_REG_AY,
149 DSP_REG_YX,
150 AX_INC_N,
151 AY_INC_N,
152 AXY_INC_N,
153 AYX_INC_N,
154 AX_IND_N,
155 AY_IND_N,
156 AXY_IND_N,
157 AYX_IND_N,
158 AX_PMOD_N,
159 AXY_PMOD_N,
160 AY_PMOD_N,
161 AYX_PMOD_N,
162 AS_DEC_N,
163 AS_INC_N,
164 AS_IND_N,
165 AS_PMOD_N,
166 A_A0,
167 A_X0,
168 A_X1,
169 A_Y0,
170 A_Y1,
171 A_SSR,
172 A_SPC,
173 A_SGR,
174 A_DBR,
175 F_REG_N,
176 F_REG_M,
177 D_REG_N,
178 D_REG_M,
179 X_REG_N,
180 X_REG_M,
181 DX_REG_N,
182 DX_REG_M,
183 V_REG_N,
184 V_REG_M,
185 XMTRX_M4,
186 F_FR0,
187 FPUL_N,
188 FPUL_M,
189 FPSCR_N,
190 FPSCR_M
191 }
192sh_arg_type;
193
194typedef enum
195 {
196 A_A1_NUM = 5,
197 A_A0_NUM = 7,
198 A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
199 A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
200 }
201sh_dsp_reg_nums;
202
203#define arch_sh1_base 0x0001
204#define arch_sh2_base 0x0002
205#define arch_sh3_base 0x0004
206#define arch_sh4_base 0x0008
207#define arch_sh4a_base 0x0010
208#define arch_sh2a_base 0x0020
209
210
211
212#define arch_op32 0x00100000
213
214#define arch_sh_no_mmu 0x04000000
215#define arch_sh_has_mmu 0x08000000
216#define arch_sh_no_co 0x10000000
217#define arch_sh_sp_fpu 0x20000000
218#define arch_sh_dp_fpu 0x40000000
219#define arch_sh_has_dsp 0x80000000
220
221
222#define arch_sh_base_mask 0x0000003f
223#define arch_opann_mask 0x00100000
224#define arch_sh_mmu_mask 0x0c000000
225#define arch_sh_co_mask 0xf0000000
226
227
228#define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
229#define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
230#define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
231#define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
232#define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
233#define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
234#define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
235#define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
236#define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
237#define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
238#define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
239#define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
240#define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
241#define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
242#define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
243#define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
244
245#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
246#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
247#define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0)
248#define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0)
249#define SH_VALID_ARCH_SET(SET) \
250 (SH_VALID_BASE_ARCH_SET (SET) \
251 && SH_VALID_MMU_ARCH_SET (SET) \
252 && SH_VALID_CO_ARCH_SET (SET))
253#define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
254 SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))
255
256#define SH_ARCH_SET_HAS_FPU(SET) \
257 (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
258#define SH_ARCH_SET_HAS_DSP(SET) \
259 (((SET) & arch_sh_has_dsp) != 0)
260
261
262
263
264
265#define SH_ARCH_UNKNOWN_ARCH 0xffffffff
266
267
268unsigned int sh_get_arch_from_bfd_mach (unsigned long mach);
269unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach);
270unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set);
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301#define arch_sh1_up (arch_sh1 | arch_sh2_up)
302#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
303#define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
304#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
305#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
306#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
307#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
308
309
310#define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
311#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
312#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
313#define arch_sh4a_up (arch_sh4a)
314
315
316#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
317#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
318#define arch_sh4al_dsp_up (arch_sh4al_dsp)
319
320
321#define arch_sh2a_up (arch_sh2a)
322#define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
323
324
325typedef struct
326{
327 const char *name;
328 sh_arg_type arg[4];
329 sh_nibble_type nibbles[9];
330 unsigned int arch;
331} sh_opcode_info;
332
333#ifdef DEFINE_TABLE
334
335const sh_opcode_info sh_table[] =
336 {
337{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
338
339{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
340
341{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up},
342
343{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
344
345{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
346
347{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
348
349{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
350
351{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
352
353{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up},
354
355{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up},
356
357{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up},
358
359{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
360
361{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
362
363{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
364
365{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
366
367{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
368
369{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
370
371{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
372
373{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
374
375{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
376
377{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
378
379{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up},
380
381{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up},
382
383{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up},
384
385{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up},
386
387{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up},
388
389{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up},
390
391{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up},
392
393{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up},
394
395{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up},
396
397{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up},
398
399{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up},
400
401{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up},
402
403{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up},
404
405{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
406
407{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
408
409{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
410
411{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
412
413{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up},
414
415{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
416
417{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
418
419{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
420
421{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
422
423{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
424
425{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},
426
427{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},
428
429{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},
430
431{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},
432
433{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
434
435{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},
436
437{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up},
438
439{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up},
440
441{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
442
443{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
444
445{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
446
447{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
448
449{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},
450
451{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},
452
453{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},
454
455{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
456
457{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
458
459{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
460{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
461
462{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
463
464{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
465
466{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
467
468{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up},
469
470{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up},
471
472{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
473
474{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
475
476{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
477
478{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
479
480{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
481
482{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
483
484{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
485
486{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
487
488{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
489
490{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up},
491
492{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up},
493
494{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},
495
496{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},
497
498{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},
499
500{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},
501
502{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},
503
504{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
505
506{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
507
508{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
509
510{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
511
512{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
513
514{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
515
516{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
517
518{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up},
519
520{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up},
521
522{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
523
524{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
525
526{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
527
528{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
529
530{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up},
531
532{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
533
534{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
535
536{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
537
538{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},
539{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},
540
541{"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
542
543{"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
544{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
545
546{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
547
548{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up},
549
550{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
551
552{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
553
554{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
555
556{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
557
558{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up},
559
560{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up},
561
562{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
563
564{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
565
566{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},
567{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up},
568
569{"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
570
571{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
572{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
573
574{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up},
575
576{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
577
578{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
579
580{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
581
582{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
583
584{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up},
585
586{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up},
587
588{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
589
590{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
591
592{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
593
594{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up},
595{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up},
596
597{"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
598
599{"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
600{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
601{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
602
603{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
604{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
605
606{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
607
608{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
609{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
610
611{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
612{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
613
614{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up},
615
616{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
617{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
618
619{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up},
620
621{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up},
622
623{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
624
625{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
626{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
627
628{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
629
630{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
631
632
633{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
634
635{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
636
637{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
638
639{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
640
641{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
642
643{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
644
645{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up},
646
647{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up},
648
649{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up},
650
651{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up},
652
653{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
654
655{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
656{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
657
658{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
659{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
660
661{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
662
663{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
664
665{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
666
667{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
668
669{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
670
671{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
672
673{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
674
675{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up},
676
677{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up},
678
679{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up},
680
681{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up},
682
683{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up},
684
685{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up},
686
687{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up},
688
689{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up},
690
691{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up},
692
693{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up},
694
695{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up},
696
697{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up},
698
699{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up},
700
701{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up},
702
703{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
704
705{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
706
707{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up},
708
709{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up},
710
711{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
712
713{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
714
715{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up},
716
717 {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
718
719{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up},
720
721{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up},
722
723{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up},
724
725{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up},
726
727{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up},
728
729{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up},
730
731{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up},
732
733{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
734
735{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
736
737{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
738
739{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up},
740
741{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up},
742
743{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up},
744
745{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up},
746
747{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
748
749{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
750
751{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
752
753{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
754
755{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
756
757{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
758
759{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
760
761{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
762
763{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
764
765{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up},
766
767{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up},
768
769{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
770
771{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
772
773{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up},
774
775{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up},
776
777{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up},
778
779{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
780
781{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
782
783{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
784
785{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
786
787{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up},
788
789{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up},
790
791{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up},
792
793{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
794
795{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
796
797{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
798
799{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
800
801{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
802
803{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
804
805{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
806
807{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
808
809{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
810
811{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
812
813{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
814
815{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up},
816
817{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up},
818
819{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up},
820
821{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up},
822
823{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up},
824
825{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up},
826
827{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up},
828
829 {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
830
831 {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
832
833 {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
834
835 {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
836
837 {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
838
839 {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
840
841 {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
842
843 {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
844
845 {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
846
847 {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
848
849 {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
850
851 {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
852
853 {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
854
855 {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
856
857 {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
858
859 {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
860
861 {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
862 {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
863 {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
864 {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
865 {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
866 {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
867 {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
868 {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
869
870 {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
871{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
872{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
873 {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
874{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
875{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
876
877 {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
878{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
879{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
880 {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
881{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
882{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
883
884 {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
885 {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
886 {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
887 {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
888 {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
889 {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
890
891 {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
892{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
893{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
894 {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
895{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
896{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
897
898 {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
899{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
900{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
901 {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
902{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
903{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
904
905 {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
906
907{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
908
909{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
910
911{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
912
913{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
914
915{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
916
917{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
918
919{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
920
921{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
922
923{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
924
925{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
926
927{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
928
929{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
930
931{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
932
933{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
934{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
935
936
937{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
938 {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
939
940{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
941 {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
942
943{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
944
945{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
946
947{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
948
949{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
950
951{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
952
953{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
954
955{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
956
957{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
958
959{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
960
961{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
962
963{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
964
965{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
966
967{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
968
969{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
970
971{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
972
973{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
974
975{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
976
977{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
978
979{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
980
981{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
982
983{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
984
985{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
986
987{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
988
989{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
990{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
991
992{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
993{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
994
995{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
996{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
997
998{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
999{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
1000
1001{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
1002
1003{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
1004
1005{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
1006{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
1007
1008{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
1009
1010{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
1011
1012{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
1013
1014{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
1015
1016{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
1017{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
1018
1019{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
1020
1021{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
1022{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
1023
1024{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1025{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1026
1027{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1028{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1029
1030{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1031{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1032
1033{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1034{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1035
1036{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1037{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1038
1039{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1040{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1041
1042{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1043
1044{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1045
1046{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1047
1048{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1049
1050{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1051
1052{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1053
1054{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1055
1056{"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1057
1058{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1059
1060{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1061
1062{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1063
1064{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1065
1066{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1067
1068{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1069
1070{"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1071
1072{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
1073
1074{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
1075{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
1076
1077{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
1078{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
1079
1080{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
1081
1082{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
1083
1084{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
1085
1086{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
1087
1088{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
1089{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
1090
1091{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
1092
1093{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
1094
1095{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
1096{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
1097
1098{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
1099{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
1100
1101{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
1102
1103 {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1104
1105{"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1106 {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1107
1108{"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1109 {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1110
1111{"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1112 {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1113
1114{"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1115 {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up},
1116 {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up},
1117 {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up},
1118 {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up},
1119 {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up},
1120 {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up},
1121 {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up},
1122 {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up},
1123 {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up},
1124 {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up},
1125 {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up},
1126 {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up},
1127 {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up},
1128 {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up},
1129 {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up},
1130 {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up},
1131 {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up},
1132 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up},
1133 {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up},
1134 {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up},
1135
1136
1137{"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1138
1139{"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1140
1141{"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1142
1143{"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1144
1145{"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1146
1147{"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1148
1149{"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
1150
1151{"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
1152
1153{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
1154
1155{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
1156
1157{ 0, {0}, {0}, 0 }
1158};
1159
1160#endif
1161
1162#ifdef ARCH_all
1163#define INCLUDE_SHMEDIA
1164#endif
1165
1166static void
1167print_movxy (const sh_opcode_info *op, int rn, int rm,
1168 fprintf_function fprintf_fn, void *stream)
1169{
1170 int n;
1171
1172 fprintf_fn (stream, "%s\t", op->name);
1173 for (n = 0; n < 2; n++)
1174 {
1175 switch (op->arg[n])
1176 {
1177 case A_IND_N:
1178 case AX_IND_N:
1179 case AXY_IND_N:
1180 case AY_IND_N:
1181 case AYX_IND_N:
1182 fprintf_fn (stream, "@r%d", rn);
1183 break;
1184 case A_INC_N:
1185 case AX_INC_N:
1186 case AXY_INC_N:
1187 case AY_INC_N:
1188 case AYX_INC_N:
1189 fprintf_fn (stream, "@r%d+", rn);
1190 break;
1191 case AX_PMOD_N:
1192 case AXY_PMOD_N:
1193 fprintf_fn (stream, "@r%d+r8", rn);
1194 break;
1195 case AY_PMOD_N:
1196 case AYX_PMOD_N:
1197 fprintf_fn (stream, "@r%d+r9", rn);
1198 break;
1199 case DSP_REG_A_M:
1200 fprintf_fn (stream, "a%c", '0' + rm);
1201 break;
1202 case DSP_REG_X:
1203 fprintf_fn (stream, "x%c", '0' + rm);
1204 break;
1205 case DSP_REG_Y:
1206 fprintf_fn (stream, "y%c", '0' + rm);
1207 break;
1208 case DSP_REG_AX:
1209 fprintf_fn (stream, "%c%c",
1210 (rm & 1) ? 'x' : 'a',
1211 (rm & 2) ? '1' : '0');
1212 break;
1213 case DSP_REG_XY:
1214 fprintf_fn (stream, "%c%c",
1215 (rm & 1) ? 'y' : 'x',
1216 (rm & 2) ? '1' : '0');
1217 break;
1218 case DSP_REG_AY:
1219 fprintf_fn (stream, "%c%c",
1220 (rm & 2) ? 'y' : 'a',
1221 (rm & 1) ? '1' : '0');
1222 break;
1223 case DSP_REG_YX:
1224 fprintf_fn (stream, "%c%c",
1225 (rm & 2) ? 'x' : 'y',
1226 (rm & 1) ? '1' : '0');
1227 break;
1228 default:
1229 abort ();
1230 }
1231 if (n == 0)
1232 fprintf_fn (stream, ",");
1233 }
1234}
1235
1236
1237
1238
1239
1240
1241static void
1242print_insn_ddt (int insn, struct disassemble_info *info)
1243{
1244 fprintf_function fprintf_fn = info->fprintf_func;
1245 void *stream = info->stream;
1246
1247
1248 if (insn == 0x000)
1249 fprintf_fn (stream, "nopx\tnopy");
1250
1251
1252
1253 if ((insn & 0x800) && (insn & 0x3ff))
1254 fprintf_fn (stream, "\t");
1255
1256
1257 if (((insn & 0xc) == 0 && (insn & 0x2a0))
1258 || ((insn & 3) == 0 && (insn & 0x150)))
1259 if (info->mach != bfd_mach_sh_dsp
1260 && info->mach != bfd_mach_sh3_dsp)
1261 {
1262 static const sh_opcode_info *first_movx, *first_movy;
1263 const sh_opcode_info *op;
1264 int is_movy;
1265
1266 if (! first_movx)
1267 {
1268 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
1269 first_movx++;
1270 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
1271 first_movy++;
1272 }
1273
1274 is_movy = ((insn & 3) != 0);
1275
1276 if (is_movy)
1277 op = first_movy;
1278 else
1279 op = first_movx;
1280
1281 while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
1282 || op->nibbles[3] != (unsigned) (insn & 0xf))
1283 op++;
1284
1285 print_movxy (op,
1286 (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
1287 + 2 * is_movy
1288 + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
1289 (insn >> 6) & 3,
1290 fprintf_fn, stream);
1291 }
1292 else
1293 fprintf_fn (stream, ".word 0x%x", insn);
1294 else
1295 {
1296 static const sh_opcode_info *first_movx, *first_movy;
1297 const sh_opcode_info *opx, *opy;
1298 unsigned int insn_x, insn_y;
1299
1300 if (! first_movx)
1301 {
1302 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
1303 first_movx++;
1304 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
1305 first_movy++;
1306 }
1307 insn_x = (insn >> 2) & 0xb;
1308 if (insn_x)
1309 {
1310 for (opx = first_movx; opx->nibbles[2] != insn_x;)
1311 opx++;
1312 print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
1313 fprintf_fn, stream);
1314 }
1315 insn_y = (insn & 3) | ((insn >> 1) & 8);
1316 if (insn_y)
1317 {
1318 if (insn_x)
1319 fprintf_fn (stream, "\t");
1320 for (opy = first_movy; opy->nibbles[2] != insn_y;)
1321 opy++;
1322 print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
1323 fprintf_fn, stream);
1324 }
1325 }
1326}
1327
1328static void
1329print_dsp_reg (int rm, fprintf_function fprintf_fn, void *stream)
1330{
1331 switch (rm)
1332 {
1333 case A_A1_NUM:
1334 fprintf_fn (stream, "a1");
1335 break;
1336 case A_A0_NUM:
1337 fprintf_fn (stream, "a0");
1338 break;
1339 case A_X0_NUM:
1340 fprintf_fn (stream, "x0");
1341 break;
1342 case A_X1_NUM:
1343 fprintf_fn (stream, "x1");
1344 break;
1345 case A_Y0_NUM:
1346 fprintf_fn (stream, "y0");
1347 break;
1348 case A_Y1_NUM:
1349 fprintf_fn (stream, "y1");
1350 break;
1351 case A_M0_NUM:
1352 fprintf_fn (stream, "m0");
1353 break;
1354 case A_A1G_NUM:
1355 fprintf_fn (stream, "a1g");
1356 break;
1357 case A_M1_NUM:
1358 fprintf_fn (stream, "m1");
1359 break;
1360 case A_A0G_NUM:
1361 fprintf_fn (stream, "a0g");
1362 break;
1363 default:
1364 fprintf_fn (stream, "0x%x", rm);
1365 break;
1366 }
1367}
1368
1369static void
1370print_insn_ppi (int field_b, struct disassemble_info *info)
1371{
1372 static const char *sx_tab[] = { "x0", "x1", "a0", "a1" };
1373 static const char *sy_tab[] = { "y0", "y1", "m0", "m1" };
1374 fprintf_function fprintf_fn = info->fprintf_func;
1375 void *stream = info->stream;
1376 unsigned int nib1, nib2, nib3;
1377 unsigned int altnib1, nib4;
1378 const char *dc = NULL;
1379 const sh_opcode_info *op;
1380
1381 if ((field_b & 0xe800) == 0)
1382 {
1383 fprintf_fn (stream, "psh%c\t#%d,",
1384 field_b & 0x1000 ? 'a' : 'l',
1385 (field_b >> 4) & 127);
1386 print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1387 return;
1388 }
1389 if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
1390 {
1391 static const char *du_tab[] = { "x0", "y0", "a0", "a1" };
1392 static const char *se_tab[] = { "x0", "x1", "y0", "a1" };
1393 static const char *sf_tab[] = { "y0", "y1", "x0", "a1" };
1394 static const char *sg_tab[] = { "m0", "m1", "a0", "a1" };
1395
1396 if (field_b & 0x2000)
1397 {
1398 fprintf_fn (stream, "p%s %s,%s,%s\t",
1399 (field_b & 0x1000) ? "add" : "sub",
1400 sx_tab[(field_b >> 6) & 3],
1401 sy_tab[(field_b >> 4) & 3],
1402 du_tab[(field_b >> 0) & 3]);
1403 }
1404 else if ((field_b & 0xf0) == 0x10
1405 && info->mach != bfd_mach_sh_dsp
1406 && info->mach != bfd_mach_sh3_dsp)
1407 {
1408 fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
1409 }
1410 else if ((field_b & 0xf3) != 0)
1411 {
1412 fprintf_fn (stream, ".word 0x%x\t", field_b);
1413 }
1414 fprintf_fn (stream, "pmuls%c%s,%s,%s",
1415 field_b & 0x2000 ? ' ' : '\t',
1416 se_tab[(field_b >> 10) & 3],
1417 sf_tab[(field_b >> 8) & 3],
1418 sg_tab[(field_b >> 2) & 3]);
1419 return;
1420 }
1421
1422 nib1 = PPIC;
1423 nib2 = field_b >> 12 & 0xf;
1424 nib3 = field_b >> 8 & 0xf;
1425 nib4 = field_b >> 4 & 0xf;
1426 switch (nib3 & 0x3)
1427 {
1428 case 0:
1429 dc = "";
1430 nib1 = PPI3;
1431 break;
1432 case 1:
1433 dc = "";
1434 break;
1435 case 2:
1436 dc = "dct ";
1437 nib3 -= 1;
1438 break;
1439 case 3:
1440 dc = "dcf ";
1441 nib3 -= 2;
1442 break;
1443 }
1444 if (nib1 == PPI3)
1445 altnib1 = PPI3NC;
1446 else
1447 altnib1 = nib1;
1448 for (op = sh_table; op->name; op++)
1449 {
1450 if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
1451 && op->nibbles[2] == nib2
1452 && op->nibbles[3] == nib3)
1453 {
1454 int n;
1455
1456 switch (op->nibbles[4])
1457 {
1458 case HEX_0:
1459 break;
1460 case HEX_XX00:
1461 if ((nib4 & 3) != 0)
1462 continue;
1463 break;
1464 case HEX_1:
1465 if ((nib4 & 3) != 1)
1466 continue;
1467 break;
1468 case HEX_00YY:
1469 if ((nib4 & 0xc) != 0)
1470 continue;
1471 break;
1472 case HEX_4:
1473 if ((nib4 & 0xc) != 4)
1474 continue;
1475 break;
1476 default:
1477 abort ();
1478 }
1479 fprintf_fn (stream, "%s%s\t", dc, op->name);
1480 for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1481 {
1482 if (n && op->arg[1] != A_END)
1483 fprintf_fn (stream, ",");
1484 switch (op->arg[n])
1485 {
1486 case DSP_REG_N:
1487 print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1488 break;
1489 case DSP_REG_X:
1490 fprintf_fn (stream, "%s", sx_tab[(field_b >> 6) & 3]);
1491 break;
1492 case DSP_REG_Y:
1493 fprintf_fn (stream, "%s", sy_tab[(field_b >> 4) & 3]);
1494 break;
1495 case A_MACH:
1496 fprintf_fn (stream, "mach");
1497 break;
1498 case A_MACL:
1499 fprintf_fn (stream, "macl");
1500 break;
1501 default:
1502 abort ();
1503 }
1504 }
1505 return;
1506 }
1507 }
1508
1509 fprintf_fn (stream, ".word 0x%x", field_b);
1510}
1511
1512
1513
1514int
1515print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
1516{
1517 fprintf_function fprintf_fn = info->fprintf_func;
1518 void *stream = info->stream;
1519 unsigned char insn[4];
1520 unsigned char nibs[8];
1521 int status;
1522 bfd_vma relmask = ~(bfd_vma) 0;
1523 const sh_opcode_info *op;
1524 unsigned int target_arch;
1525 int allow_op32;
1526
1527 switch (info->mach)
1528 {
1529 case bfd_mach_sh:
1530 target_arch = arch_sh1;
1531 break;
1532 case bfd_mach_sh4:
1533 target_arch = arch_sh4;
1534 break;
1535 case bfd_mach_sh5:
1536#ifdef INCLUDE_SHMEDIA
1537 status = print_insn_sh64 (memaddr, info);
1538 if (status != -2)
1539 return status;
1540#endif
1541
1542
1543 target_arch = arch_sh4;
1544 break;
1545 default:
1546 fprintf (stderr, "sh architecture not supported\n");
1547 return -1;
1548 }
1549
1550 status = info->read_memory_func (memaddr, insn, 2, info);
1551
1552 if (status != 0)
1553 {
1554 info->memory_error_func (status, memaddr, info);
1555 return -1;
1556 }
1557
1558 if (info->endian == BFD_ENDIAN_LITTLE)
1559 {
1560 nibs[0] = (insn[1] >> 4) & 0xf;
1561 nibs[1] = insn[1] & 0xf;
1562
1563 nibs[2] = (insn[0] >> 4) & 0xf;
1564 nibs[3] = insn[0] & 0xf;
1565 }
1566 else
1567 {
1568 nibs[0] = (insn[0] >> 4) & 0xf;
1569 nibs[1] = insn[0] & 0xf;
1570
1571 nibs[2] = (insn[1] >> 4) & 0xf;
1572 nibs[3] = insn[1] & 0xf;
1573 }
1574 status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
1575 if (status != 0)
1576 allow_op32 = 0;
1577 else
1578 {
1579 allow_op32 = 1;
1580
1581 if (info->endian == BFD_ENDIAN_LITTLE)
1582 {
1583 nibs[4] = (insn[3] >> 4) & 0xf;
1584 nibs[5] = insn[3] & 0xf;
1585
1586 nibs[6] = (insn[2] >> 4) & 0xf;
1587 nibs[7] = insn[2] & 0xf;
1588 }
1589 else
1590 {
1591 nibs[4] = (insn[2] >> 4) & 0xf;
1592 nibs[5] = insn[2] & 0xf;
1593
1594 nibs[6] = (insn[3] >> 4) & 0xf;
1595 nibs[7] = insn[3] & 0xf;
1596 }
1597 }
1598
1599 if (nibs[0] == 0xf && (nibs[1] & 4) == 0
1600 && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
1601 {
1602 if (nibs[1] & 8)
1603 {
1604 int field_b;
1605
1606 status = info->read_memory_func (memaddr + 2, insn, 2, info);
1607
1608 if (status != 0)
1609 {
1610 info->memory_error_func (status, memaddr + 2, info);
1611 return -1;
1612 }
1613
1614 if (info->endian == BFD_ENDIAN_LITTLE)
1615 field_b = insn[1] << 8 | insn[0];
1616 else
1617 field_b = insn[0] << 8 | insn[1];
1618
1619 print_insn_ppi (field_b, info);
1620 print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1621 return 4;
1622 }
1623 print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1624 return 2;
1625 }
1626 for (op = sh_table; op->name; op++)
1627 {
1628 int n;
1629 int imm = 0;
1630 int rn = 0;
1631 int rm = 0;
1632 int rb = 0;
1633 int disp_pc;
1634 bfd_vma disp_pc_addr = 0;
1635 int disp = 0;
1636 int has_disp = 0;
1637 int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
1638
1639 if (!allow_op32
1640 && SH_MERGE_ARCH_SET (op->arch, arch_op32))
1641 goto fail;
1642
1643 if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
1644 goto fail;
1645 for (n = 0; n < max_n; n++)
1646 {
1647 int i = op->nibbles[n];
1648
1649 if (i < 16)
1650 {
1651 if (nibs[n] == i)
1652 continue;
1653 goto fail;
1654 }
1655 switch (i)
1656 {
1657 case BRANCH_8:
1658 imm = (nibs[2] << 4) | (nibs[3]);
1659 if (imm & 0x80)
1660 imm |= ~0xff;
1661 imm = ((char) imm) * 2 + 4;
1662 goto ok;
1663 case BRANCH_12:
1664 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
1665 if (imm & 0x800)
1666 imm |= ~0xfff;
1667 imm = imm * 2 + 4;
1668 goto ok;
1669 case IMM0_3c:
1670 if (nibs[3] & 0x8)
1671 goto fail;
1672 imm = nibs[3] & 0x7;
1673 break;
1674 case IMM0_3s:
1675 if (!(nibs[3] & 0x8))
1676 goto fail;
1677 imm = nibs[3] & 0x7;
1678 break;
1679 case IMM0_3Uc:
1680 if (nibs[2] & 0x8)
1681 goto fail;
1682 imm = nibs[2] & 0x7;
1683 break;
1684 case IMM0_3Us:
1685 if (!(nibs[2] & 0x8))
1686 goto fail;
1687 imm = nibs[2] & 0x7;
1688 break;
1689 case DISP0_12:
1690 case DISP1_12:
1691 disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
1692 has_disp = 1;
1693 goto ok;
1694 case DISP0_12BY2:
1695 case DISP1_12BY2:
1696 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
1697 relmask = ~(bfd_vma) 1;
1698 has_disp = 1;
1699 goto ok;
1700 case DISP0_12BY4:
1701 case DISP1_12BY4:
1702 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
1703 relmask = ~(bfd_vma) 3;
1704 has_disp = 1;
1705 goto ok;
1706 case DISP0_12BY8:
1707 case DISP1_12BY8:
1708 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
1709 relmask = ~(bfd_vma) 7;
1710 has_disp = 1;
1711 goto ok;
1712 case IMM0_20_4:
1713 break;
1714 case IMM0_20:
1715 imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1716 | (nibs[6] << 4) | nibs[7]);
1717 if (imm & 0x80000)
1718 imm -= 0x100000;
1719 goto ok;
1720 case IMM0_20BY8:
1721 imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1722 | (nibs[6] << 4) | nibs[7]);
1723 imm <<= 8;
1724 if (imm & 0x8000000)
1725 imm -= 0x10000000;
1726 goto ok;
1727 case IMM0_4:
1728 case IMM1_4:
1729 imm = nibs[3];
1730 goto ok;
1731 case IMM0_4BY2:
1732 case IMM1_4BY2:
1733 imm = nibs[3] << 1;
1734 goto ok;
1735 case IMM0_4BY4:
1736 case IMM1_4BY4:
1737 imm = nibs[3] << 2;
1738 goto ok;
1739 case IMM0_8:
1740 case IMM1_8:
1741 imm = (nibs[2] << 4) | nibs[3];
1742 disp = imm;
1743 has_disp = 1;
1744 if (imm & 0x80)
1745 imm -= 0x100;
1746 goto ok;
1747 case PCRELIMM_8BY2:
1748 imm = ((nibs[2] << 4) | nibs[3]) << 1;
1749 relmask = ~(bfd_vma) 1;
1750 goto ok;
1751 case PCRELIMM_8BY4:
1752 imm = ((nibs[2] << 4) | nibs[3]) << 2;
1753 relmask = ~(bfd_vma) 3;
1754 goto ok;
1755 case IMM0_8BY2:
1756 case IMM1_8BY2:
1757 imm = ((nibs[2] << 4) | nibs[3]) << 1;
1758 goto ok;
1759 case IMM0_8BY4:
1760 case IMM1_8BY4:
1761 imm = ((nibs[2] << 4) | nibs[3]) << 2;
1762 goto ok;
1763 case REG_N_D:
1764 if ((nibs[n] & 1) != 0)
1765 goto fail;
1766
1767 case REG_N:
1768 rn = nibs[n];
1769 break;
1770 case REG_M:
1771 rm = nibs[n];
1772 break;
1773 case REG_N_B01:
1774 if ((nibs[n] & 0x3) != 1 )
1775 goto fail;
1776 rn = (nibs[n] & 0xc) >> 2;
1777 break;
1778 case REG_NM:
1779 rn = (nibs[n] & 0xc) >> 2;
1780 rm = (nibs[n] & 0x3);
1781 break;
1782 case REG_B:
1783 rb = nibs[n] & 0x07;
1784 break;
1785 case SDT_REG_N:
1786
1787 rn = nibs[n];
1788 if ((rn & 0xc) != 4)
1789 goto fail;
1790 rn = rn & 0x3;
1791 rn |= (!(rn & 2)) << 2;
1792 break;
1793 case PPI:
1794 case REPEAT:
1795 goto fail;
1796 default:
1797 abort ();
1798 }
1799 }
1800
1801 ok:
1802
1803
1804
1805 if (target_arch == arch_sh2a
1806 && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
1807 || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
1808 goto fail;
1809
1810 fprintf_fn (stream, "%s\t", op->name);
1811 disp_pc = 0;
1812 for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1813 {
1814 if (n && op->arg[1] != A_END)
1815 fprintf_fn (stream, ",");
1816 switch (op->arg[n])
1817 {
1818 case A_IMM:
1819 fprintf_fn (stream, "#%d", imm);
1820 break;
1821 case A_R0:
1822 fprintf_fn (stream, "r0");
1823 break;
1824 case A_REG_N:
1825 fprintf_fn (stream, "r%d", rn);
1826 break;
1827 case A_INC_N:
1828 case AS_INC_N:
1829 fprintf_fn (stream, "@r%d+", rn);
1830 break;
1831 case A_DEC_N:
1832 case AS_DEC_N:
1833 fprintf_fn (stream, "@-r%d", rn);
1834 break;
1835 case A_IND_N:
1836 case AS_IND_N:
1837 fprintf_fn (stream, "@r%d", rn);
1838 break;
1839 case A_DISP_REG_N:
1840 fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
1841 break;
1842 case AS_PMOD_N:
1843 fprintf_fn (stream, "@r%d+r8", rn);
1844 break;
1845 case A_REG_M:
1846 fprintf_fn (stream, "r%d", rm);
1847 break;
1848 case A_INC_M:
1849 fprintf_fn (stream, "@r%d+", rm);
1850 break;
1851 case A_DEC_M:
1852 fprintf_fn (stream, "@-r%d", rm);
1853 break;
1854 case A_IND_M:
1855 fprintf_fn (stream, "@r%d", rm);
1856 break;
1857 case A_DISP_REG_M:
1858 fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
1859 break;
1860 case A_REG_B:
1861 fprintf_fn (stream, "r%d_bank", rb);
1862 break;
1863 case A_DISP_PC:
1864 disp_pc = 1;
1865 disp_pc_addr = imm + 4 + (memaddr & relmask);
1866 (*info->print_address_func) (disp_pc_addr, info);
1867 break;
1868 case A_IND_R0_REG_N:
1869 fprintf_fn (stream, "@(r0,r%d)", rn);
1870 break;
1871 case A_IND_R0_REG_M:
1872 fprintf_fn (stream, "@(r0,r%d)", rm);
1873 break;
1874 case A_DISP_GBR:
1875 fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
1876 break;
1877 case A_TBR:
1878 fprintf_fn (stream, "tbr");
1879 break;
1880 case A_DISP2_TBR:
1881 fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
1882 break;
1883 case A_INC_R15:
1884 fprintf_fn (stream, "@r15+");
1885 break;
1886 case A_DEC_R15:
1887 fprintf_fn (stream, "@-r15");
1888 break;
1889 case A_R0_GBR:
1890 fprintf_fn (stream, "@(r0,gbr)");
1891 break;
1892 case A_BDISP12:
1893 case A_BDISP8:
1894 {
1895 bfd_vma addr;
1896 addr = imm + memaddr;
1897 (*info->print_address_func) (addr, info);
1898 }
1899 break;
1900 case A_SR:
1901 fprintf_fn (stream, "sr");
1902 break;
1903 case A_GBR:
1904 fprintf_fn (stream, "gbr");
1905 break;
1906 case A_VBR:
1907 fprintf_fn (stream, "vbr");
1908 break;
1909 case A_DSR:
1910 fprintf_fn (stream, "dsr");
1911 break;
1912 case A_MOD:
1913 fprintf_fn (stream, "mod");
1914 break;
1915 case A_RE:
1916 fprintf_fn (stream, "re");
1917 break;
1918 case A_RS:
1919 fprintf_fn (stream, "rs");
1920 break;
1921 case A_A0:
1922 fprintf_fn (stream, "a0");
1923 break;
1924 case A_X0:
1925 fprintf_fn (stream, "x0");
1926 break;
1927 case A_X1:
1928 fprintf_fn (stream, "x1");
1929 break;
1930 case A_Y0:
1931 fprintf_fn (stream, "y0");
1932 break;
1933 case A_Y1:
1934 fprintf_fn (stream, "y1");
1935 break;
1936 case DSP_REG_M:
1937 print_dsp_reg (rm, fprintf_fn, stream);
1938 break;
1939 case A_SSR:
1940 fprintf_fn (stream, "ssr");
1941 break;
1942 case A_SPC:
1943 fprintf_fn (stream, "spc");
1944 break;
1945 case A_MACH:
1946 fprintf_fn (stream, "mach");
1947 break;
1948 case A_MACL:
1949 fprintf_fn (stream, "macl");
1950 break;
1951 case A_PR:
1952 fprintf_fn (stream, "pr");
1953 break;
1954 case A_SGR:
1955 fprintf_fn (stream, "sgr");
1956 break;
1957 case A_DBR:
1958 fprintf_fn (stream, "dbr");
1959 break;
1960 case F_REG_N:
1961 fprintf_fn (stream, "fr%d", rn);
1962 break;
1963 case F_REG_M:
1964 fprintf_fn (stream, "fr%d", rm);
1965 break;
1966 case DX_REG_N:
1967 if (rn & 1)
1968 {
1969 fprintf_fn (stream, "xd%d", rn & ~1);
1970 break;
1971 }
1972 case D_REG_N:
1973 fprintf_fn (stream, "dr%d", rn);
1974 break;
1975 case DX_REG_M:
1976 if (rm & 1)
1977 {
1978 fprintf_fn (stream, "xd%d", rm & ~1);
1979 break;
1980 }
1981 case D_REG_M:
1982 fprintf_fn (stream, "dr%d", rm);
1983 break;
1984 case FPSCR_M:
1985 case FPSCR_N:
1986 fprintf_fn (stream, "fpscr");
1987 break;
1988 case FPUL_M:
1989 case FPUL_N:
1990 fprintf_fn (stream, "fpul");
1991 break;
1992 case F_FR0:
1993 fprintf_fn (stream, "fr0");
1994 break;
1995 case V_REG_N:
1996 fprintf_fn (stream, "fv%d", rn * 4);
1997 break;
1998 case V_REG_M:
1999 fprintf_fn (stream, "fv%d", rm * 4);
2000 break;
2001 case XMTRX_M4:
2002 fprintf_fn (stream, "xmtrx");
2003 break;
2004 default:
2005 abort ();
2006 }
2007 }
2008
2009#if 0
2010
2011
2012
2013
2014
2015 if (!(info->flags & 1)
2016 && (op->name[0] == 'j'
2017 || (op->name[0] == 'b'
2018 && (op->name[1] == 'r'
2019 || op->name[1] == 's'))
2020 || (op->name[0] == 'r' && op->name[1] == 't')
2021 || (op->name[0] == 'b' && op->name[2] == '.')))
2022 {
2023 info->flags |= 1;
2024 fprintf_fn (stream, "\t(slot ");
2025 print_insn_sh (memaddr + 2, info);
2026 info->flags &= ~1;
2027 fprintf_fn (stream, ")");
2028 return 4;
2029 }
2030#endif
2031
2032 if (disp_pc && strcmp (op->name, "mova") != 0)
2033 {
2034 int size;
2035 bfd_byte bytes[4];
2036
2037 if (relmask == ~(bfd_vma) 1)
2038 size = 2;
2039 else
2040 size = 4;
2041 status = info->read_memory_func (disp_pc_addr, bytes, size, info);
2042 if (status == 0)
2043 {
2044 unsigned int val;
2045
2046 if (size == 2)
2047 {
2048 if (info->endian == BFD_ENDIAN_LITTLE)
2049 val = bfd_getl16 (bytes);
2050 else
2051 val = bfd_getb16 (bytes);
2052 }
2053 else
2054 {
2055 if (info->endian == BFD_ENDIAN_LITTLE)
2056 val = bfd_getl32 (bytes);
2057 else
2058 val = bfd_getb32 (bytes);
2059 }
2060 if ((*info->symbol_at_address_func) (val, info))
2061 {
2062 fprintf_fn (stream, "\t! ");
2063 (*info->print_address_func) (val, info);
2064 }
2065 else
2066 fprintf_fn (stream, "\t! 0x%x", val);
2067 }
2068 }
2069
2070 return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
2071 fail:
2072 ;
2073
2074 }
2075 fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
2076 return 2;
2077}
2078
