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20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/exec-all.h"
23#include "exec/memory.h"
24#include "exec/address-spaces.h"
25#include "exec/cpu_ldst.h"
26
27#include "exec/cputlb.h"
28
29#include "exec/memory-internal.h"
30#include "exec/ram_addr.h"
31#include "tcg/tcg.h"
32
33
34
35
36
37#ifdef DEBUG_TLB
38# define DEBUG_TLB_GATE 1
39# ifdef DEBUG_TLB_LOG
40# define DEBUG_TLB_LOG_GATE 1
41# else
42# define DEBUG_TLB_LOG_GATE 0
43# endif
44#else
45# define DEBUG_TLB_GATE 0
46# define DEBUG_TLB_LOG_GATE 0
47#endif
48
49#define tlb_debug(fmt, ...) do { \
50 if (DEBUG_TLB_LOG_GATE) { \
51 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
52 ## __VA_ARGS__); \
53 } else if (DEBUG_TLB_GATE) { \
54 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
55 } \
56} while (0)
57
58
59int tlb_flush_count;
60
61
62
63
64
65
66
67
68
69
70
71
72
73void tlb_flush(CPUState *cpu, int flush_global)
74{
75 CPUArchState *env = cpu->env_ptr;
76
77 tlb_debug("(%d)\n", flush_global);
78
79
80
81 cpu->current_tb = NULL;
82
83 memset(env->tlb_table, -1, sizeof(env->tlb_table));
84 memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
85 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
86
87 env->vtlb_index = 0;
88 env->tlb_flush_addr = -1;
89 env->tlb_flush_mask = 0;
90 tlb_flush_count++;
91}
92
93static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
94{
95 CPUArchState *env = cpu->env_ptr;
96
97 tlb_debug("start\n");
98
99
100 cpu->current_tb = NULL;
101
102 for (;;) {
103 int mmu_idx = va_arg(argp, int);
104
105 if (mmu_idx < 0) {
106 break;
107 }
108
109 tlb_debug("%d\n", mmu_idx);
110
111 memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
112 memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
113 }
114
115 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
116}
117
118void tlb_flush_by_mmuidx(CPUState *cpu, ...)
119{
120 va_list argp;
121 va_start(argp, cpu);
122 v_tlb_flush_by_mmuidx(cpu, argp);
123 va_end(argp);
124}
125
126static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
127{
128 if (addr == (tlb_entry->addr_read &
129 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
130 addr == (tlb_entry->addr_write &
131 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
132 addr == (tlb_entry->addr_code &
133 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
134 memset(tlb_entry, -1, sizeof(*tlb_entry));
135 }
136}
137
138void tlb_flush_page(CPUState *cpu, target_ulong addr)
139{
140 CPUArchState *env = cpu->env_ptr;
141 int i;
142 int mmu_idx;
143
144 tlb_debug("page :" TARGET_FMT_lx "\n", addr);
145
146
147 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
148 tlb_debug("forcing full flush ("
149 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
150 env->tlb_flush_addr, env->tlb_flush_mask);
151
152 tlb_flush(cpu, 1);
153 return;
154 }
155
156
157 cpu->current_tb = NULL;
158
159 addr &= TARGET_PAGE_MASK;
160 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
161 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
162 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
163 }
164
165
166 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
167 int k;
168 for (k = 0; k < CPU_VTLB_SIZE; k++) {
169 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
170 }
171 }
172
173 tb_flush_jmp_cache(cpu, addr);
174}
175
176void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
177{
178 CPUArchState *env = cpu->env_ptr;
179 int i, k;
180 va_list argp;
181
182 va_start(argp, addr);
183
184 tlb_debug("addr "TARGET_FMT_lx"\n", addr);
185
186
187 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
188 tlb_debug("forced full flush ("
189 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
190 env->tlb_flush_addr, env->tlb_flush_mask);
191
192 v_tlb_flush_by_mmuidx(cpu, argp);
193 va_end(argp);
194 return;
195 }
196
197
198 cpu->current_tb = NULL;
199
200 addr &= TARGET_PAGE_MASK;
201 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
202
203 for (;;) {
204 int mmu_idx = va_arg(argp, int);
205
206 if (mmu_idx < 0) {
207 break;
208 }
209
210 tlb_debug("idx %d\n", mmu_idx);
211
212 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
213
214
215 for (k = 0; k < CPU_VTLB_SIZE; k++) {
216 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
217 }
218 }
219 va_end(argp);
220
221 tb_flush_jmp_cache(cpu, addr);
222}
223
224
225
226void tlb_protect_code(ram_addr_t ram_addr)
227{
228 cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
229 DIRTY_MEMORY_CODE);
230}
231
232
233
234void tlb_unprotect_code(ram_addr_t ram_addr)
235{
236 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
237}
238
239static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
240{
241 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
242}
243
244void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
245 uintptr_t length)
246{
247 uintptr_t addr;
248
249 if (tlb_is_dirty_ram(tlb_entry)) {
250 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
251 if ((addr - start) < length) {
252 tlb_entry->addr_write |= TLB_NOTDIRTY;
253 }
254 }
255}
256
257static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
258{
259 ram_addr_t ram_addr;
260
261 if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
262 fprintf(stderr, "Bad ram pointer %p\n", ptr);
263 abort();
264 }
265 return ram_addr;
266}
267
268void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
269{
270 CPUArchState *env;
271
272 int mmu_idx;
273
274 env = cpu->env_ptr;
275 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
276 unsigned int i;
277
278 for (i = 0; i < CPU_TLB_SIZE; i++) {
279 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
280 start1, length);
281 }
282
283 for (i = 0; i < CPU_VTLB_SIZE; i++) {
284 tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
285 start1, length);
286 }
287 }
288}
289
290static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
291{
292 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
293 tlb_entry->addr_write = vaddr;
294 }
295}
296
297
298
299void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
300{
301 CPUArchState *env = cpu->env_ptr;
302 int i;
303 int mmu_idx;
304
305 vaddr &= TARGET_PAGE_MASK;
306 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
307 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
308 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
309 }
310
311 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
312 int k;
313 for (k = 0; k < CPU_VTLB_SIZE; k++) {
314 tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
315 }
316 }
317}
318
319
320
321static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
322 target_ulong size)
323{
324 target_ulong mask = ~(size - 1);
325
326 if (env->tlb_flush_addr == (target_ulong)-1) {
327 env->tlb_flush_addr = vaddr & mask;
328 env->tlb_flush_mask = mask;
329 return;
330 }
331
332
333
334 mask &= env->tlb_flush_mask;
335 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
336 mask <<= 1;
337 }
338 env->tlb_flush_addr &= mask;
339 env->tlb_flush_mask = mask;
340}
341
342
343
344
345
346
347
348
349void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
350 hwaddr paddr, MemTxAttrs attrs, int prot,
351 int mmu_idx, target_ulong size)
352{
353 CPUArchState *env = cpu->env_ptr;
354 MemoryRegionSection *section;
355 unsigned int index;
356 target_ulong address;
357 target_ulong code_address;
358 uintptr_t addend;
359 CPUTLBEntry *te;
360 hwaddr iotlb, xlat, sz;
361 unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
362 int asidx = cpu_asidx_from_attrs(cpu, attrs);
363
364 assert(size >= TARGET_PAGE_SIZE);
365 if (size != TARGET_PAGE_SIZE) {
366 tlb_add_large_page(env, vaddr, size);
367 }
368
369 sz = size;
370 section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
371 assert(sz >= TARGET_PAGE_SIZE);
372
373 tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
374 " prot=%x idx=%d\n",
375 vaddr, paddr, prot, mmu_idx);
376
377 address = vaddr;
378 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
379
380 address |= TLB_MMIO;
381 addend = 0;
382 } else {
383
384 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
385 }
386
387 code_address = address;
388 iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
389 prot, &address);
390
391 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
392 te = &env->tlb_table[mmu_idx][index];
393
394
395 env->tlb_v_table[mmu_idx][vidx] = *te;
396 env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
397
398
399 env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
400 env->iotlb[mmu_idx][index].attrs = attrs;
401 te->addend = addend - vaddr;
402 if (prot & PAGE_READ) {
403 te->addr_read = address;
404 } else {
405 te->addr_read = -1;
406 }
407
408 if (prot & PAGE_EXEC) {
409 te->addr_code = code_address;
410 } else {
411 te->addr_code = -1;
412 }
413 if (prot & PAGE_WRITE) {
414 if ((memory_region_is_ram(section->mr) && section->readonly)
415 || memory_region_is_romd(section->mr)) {
416
417 te->addr_write = address | TLB_MMIO;
418 } else if (memory_region_is_ram(section->mr)
419 && cpu_physical_memory_is_clean(
420 memory_region_get_ram_addr(section->mr) + xlat)) {
421 te->addr_write = address | TLB_NOTDIRTY;
422 } else {
423 te->addr_write = address;
424 }
425 } else {
426 te->addr_write = -1;
427 }
428}
429
430
431
432
433void tlb_set_page(CPUState *cpu, target_ulong vaddr,
434 hwaddr paddr, int prot,
435 int mmu_idx, target_ulong size)
436{
437 tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,
438 prot, mmu_idx, size);
439}
440
441
442
443
444
445
446tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
447{
448 int mmu_idx, page_index, pd;
449 void *p;
450 MemoryRegion *mr;
451 CPUState *cpu = ENV_GET_CPU(env1);
452 CPUIOTLBEntry *iotlbentry;
453
454 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
455 mmu_idx = cpu_mmu_index(env1, true);
456 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
457 (addr & TARGET_PAGE_MASK))) {
458 cpu_ldub_code(env1, addr);
459 }
460 iotlbentry = &env1->iotlb[mmu_idx][page_index];
461 pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
462 mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
463 if (memory_region_is_unassigned(mr)) {
464 CPUClass *cc = CPU_GET_CLASS(cpu);
465
466 if (cc->do_unassigned_access) {
467 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
468 } else {
469 cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
470 TARGET_FMT_lx "\n", addr);
471 }
472 }
473 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
474 return qemu_ram_addr_from_host_nofail(p);
475}
476
477#define MMUSUFFIX _mmu
478
479#define SHIFT 0
480#include "softmmu_template.h"
481
482#define SHIFT 1
483#include "softmmu_template.h"
484
485#define SHIFT 2
486#include "softmmu_template.h"
487
488#define SHIFT 3
489#include "softmmu_template.h"
490#undef MMUSUFFIX
491
492#define MMUSUFFIX _cmmu
493#undef GETPC_ADJ
494#define GETPC_ADJ 0
495#undef GETRA
496#define GETRA() ((uintptr_t)0)
497#define SOFTMMU_CODE_ACCESS
498
499#define SHIFT 0
500#include "softmmu_template.h"
501
502#define SHIFT 1
503#include "softmmu_template.h"
504
505#define SHIFT 2
506#include "softmmu_template.h"
507
508#define SHIFT 3
509#include "softmmu_template.h"
510