LXR uboot/arch/mips/mach-mscc/dram.c

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8#include <asm/global_data.h>
   9
  10#include <asm/io.h>
  11#include <asm/types.h>
  12
  13#include <mach/tlb.h>
  14#include <mach/ddr.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18static inline int vcoreiii_train_bytelane(void)
  19{
  20        int ret;
  21
  22        ret = hal_vcoreiii_train_bytelane(0);
  23
  24#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
  25        defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
  26        if (ret)
  27                return ret;
  28        ret = hal_vcoreiii_train_bytelane(1);
  29#endif
  30
  31        return ret;
  32}
  33
  34int vcoreiii_ddr_init(void)
  35{
  36        register int res;
  37
  38        if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
  39              & ICPU_MEMCTRL_STAT_INIT_DONE)) {
  40                hal_vcoreiii_init_memctl();
  41                hal_vcoreiii_wait_memctl();
  42                if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
  43                        hal_vcoreiii_ddr_failed();
  44        }
  45
  46        res = dram_check();
  47        if (res == 0)
  48                hal_vcoreiii_ddr_verified();
  49        else
  50                hal_vcoreiii_ddr_failed();
  51
  52        /*  Remap DDR to kuseg: Clear boot-mode */
  53        clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  54                     ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
  55        /* - and read-back to activate/verify */
  56        readl(BASE_CFG + ICPU_GENERAL_CTRL);
  57
  58        return res;
  59}
  60
  61int print_cpuinfo(void)
  62{
  63        printf("MSCC VCore-III MIPS 24Kec\n");
  64
  65        return 0;
  66}
  67
  68int dram_init(void)
  69{
  70        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  71        return 0;
  72}
  73