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19#include "qemu/osdep.h"
20#include "cpu.h"
21#include "trace.h"
22#include "disas/disas.h"
23#include "tcg.h"
24#include "qemu/atomic.h"
25#include "sysemu/qtest.h"
26#include "qemu/timer.h"
27#include "exec/address-spaces.h"
28#include "qemu/rcu.h"
29#include "exec/tb-hash.h"
30#include "exec/log.h"
31#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
32#include "hw/i386/apic.h"
33#endif
34#include "sysemu/replay.h"
35
36
37
38typedef struct SyncClocks {
39 int64_t diff_clk;
40 int64_t last_cpu_icount;
41 int64_t realtime_clock;
42} SyncClocks;
43
44#if !defined(CONFIG_USER_ONLY)
45
46
47
48
49#define VM_CLOCK_ADVANCE 3000000
50#define THRESHOLD_REDUCE 1.5
51#define MAX_DELAY_PRINT_RATE 2000000000LL
52#define MAX_NB_PRINTS 100
53
54static void align_clocks(SyncClocks *sc, const CPUState *cpu)
55{
56 int64_t cpu_icount;
57
58 if (!icount_align_option) {
59 return;
60 }
61
62 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
63 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
64 sc->last_cpu_icount = cpu_icount;
65
66 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
67#ifndef _WIN32
68 struct timespec sleep_delay, rem_delay;
69 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
70 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
71 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
72 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
73 } else {
74 sc->diff_clk = 0;
75 }
76#else
77 Sleep(sc->diff_clk / SCALE_MS);
78 sc->diff_clk = 0;
79#endif
80 }
81}
82
83static void print_delay(const SyncClocks *sc)
84{
85 static float threshold_delay;
86 static int64_t last_realtime_clock;
87 static int nb_prints;
88
89 if (icount_align_option &&
90 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
91 nb_prints < MAX_NB_PRINTS) {
92 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
93 (-sc->diff_clk / (float)1000000000LL <
94 (threshold_delay - THRESHOLD_REDUCE))) {
95 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
96 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
97 threshold_delay - 1,
98 threshold_delay);
99 nb_prints++;
100 last_realtime_clock = sc->realtime_clock;
101 }
102 }
103}
104
105static void init_delay_params(SyncClocks *sc,
106 const CPUState *cpu)
107{
108 if (!icount_align_option) {
109 return;
110 }
111 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
112 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
113 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
114 if (sc->diff_clk < max_delay) {
115 max_delay = sc->diff_clk;
116 }
117 if (sc->diff_clk > max_advance) {
118 max_advance = sc->diff_clk;
119 }
120
121
122
123 print_delay(sc);
124}
125#else
126static void align_clocks(SyncClocks *sc, const CPUState *cpu)
127{
128}
129
130static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
131{
132}
133#endif
134
135
136static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
137{
138 CPUArchState *env = cpu->env_ptr;
139 uintptr_t next_tb;
140 uint8_t *tb_ptr = itb->tc_ptr;
141
142 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
143 "Trace %p [" TARGET_FMT_lx "] %s\n",
144 itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
145
146#if defined(DEBUG_DISAS)
147 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
148#if defined(TARGET_I386)
149 log_cpu_state(cpu, CPU_DUMP_CCOP);
150#elif defined(TARGET_M68K)
151
152 cpu_m68k_flush_flags(env, env->cc_op);
153 env->cc_op = CC_OP_FLAGS;
154 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
155 log_cpu_state(cpu, 0);
156#else
157 log_cpu_state(cpu, 0);
158#endif
159 }
160#endif
161
162 cpu->can_do_io = !use_icount;
163 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
164 cpu->can_do_io = 1;
165 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
166 next_tb & TB_EXIT_MASK);
167
168 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
169
170
171
172
173 CPUClass *cc = CPU_GET_CLASS(cpu);
174 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
175 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
176 "Stopped execution of TB chain before %p ["
177 TARGET_FMT_lx "] %s\n",
178 itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
179 if (cc->synchronize_from_tb) {
180 cc->synchronize_from_tb(cpu, tb);
181 } else {
182 assert(cc->set_pc);
183 cc->set_pc(cpu, tb->pc);
184 }
185 }
186 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
187
188
189
190 cpu->tcg_exit_req = 0;
191 }
192 return next_tb;
193}
194
195
196
197static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
198 TranslationBlock *orig_tb, bool ignore_icount)
199{
200 TranslationBlock *tb;
201
202
203
204 if (max_cycles > CF_COUNT_MASK)
205 max_cycles = CF_COUNT_MASK;
206
207 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
208 max_cycles | CF_NOCACHE
209 | (ignore_icount ? CF_IGNORE_ICOUNT : 0));
210 tb->orig_tb = tcg_ctx.tb_ctx.tb_invalidated_flag ? NULL : orig_tb;
211 cpu->current_tb = tb;
212
213 trace_exec_tb_nocache(tb, tb->pc);
214 cpu_tb_exec(cpu, tb);
215 cpu->current_tb = NULL;
216 tb_phys_invalidate(tb, -1);
217 tb_free(tb);
218}
219
220static TranslationBlock *tb_find_physical(CPUState *cpu,
221 target_ulong pc,
222 target_ulong cs_base,
223 uint64_t flags)
224{
225 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
226 TranslationBlock *tb, **ptb1;
227 unsigned int h;
228 tb_page_addr_t phys_pc, phys_page1;
229 target_ulong virt_page2;
230
231 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
232
233
234 phys_pc = get_page_addr_code(env, pc);
235 phys_page1 = phys_pc & TARGET_PAGE_MASK;
236 h = tb_phys_hash_func(phys_pc);
237 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
238 for(;;) {
239 tb = *ptb1;
240 if (!tb) {
241 return NULL;
242 }
243 if (tb->pc == pc &&
244 tb->page_addr[0] == phys_page1 &&
245 tb->cs_base == cs_base &&
246 tb->flags == flags) {
247
248 if (tb->page_addr[1] != -1) {
249 tb_page_addr_t phys_page2;
250
251 virt_page2 = (pc & TARGET_PAGE_MASK) +
252 TARGET_PAGE_SIZE;
253 phys_page2 = get_page_addr_code(env, virt_page2);
254 if (tb->page_addr[1] == phys_page2) {
255 break;
256 }
257 } else {
258 break;
259 }
260 }
261 ptb1 = &tb->phys_hash_next;
262 }
263
264
265 *ptb1 = tb->phys_hash_next;
266 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
267 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
268 return tb;
269}
270
271static TranslationBlock *tb_find_slow(CPUState *cpu,
272 target_ulong pc,
273 target_ulong cs_base,
274 uint64_t flags)
275{
276 TranslationBlock *tb;
277
278 tb = tb_find_physical(cpu, pc, cs_base, flags);
279 if (tb) {
280 goto found;
281 }
282
283#ifdef CONFIG_USER_ONLY
284
285
286
287
288
289 tb_unlock();
290 mmap_lock();
291 tb_lock();
292 tb = tb_find_physical(cpu, pc, cs_base, flags);
293 if (tb) {
294 mmap_unlock();
295 goto found;
296 }
297#endif
298
299
300 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
301
302#ifdef CONFIG_USER_ONLY
303 mmap_unlock();
304#endif
305
306found:
307
308 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
309 return tb;
310}
311
312static inline TranslationBlock *tb_find_fast(CPUState *cpu)
313{
314 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
315 TranslationBlock *tb;
316 target_ulong cs_base, pc;
317 int flags;
318
319
320
321
322 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
323 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
324 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
325 tb->flags != flags)) {
326 tb = tb_find_slow(cpu, pc, cs_base, flags);
327 }
328 return tb;
329}
330
331static void cpu_handle_debug_exception(CPUState *cpu)
332{
333 CPUClass *cc = CPU_GET_CLASS(cpu);
334 CPUWatchpoint *wp;
335
336 if (!cpu->watchpoint_hit) {
337 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
338 wp->flags &= ~BP_WATCHPOINT_HIT;
339 }
340 }
341
342 cc->debug_excp_handler(cpu);
343}
344
345
346
347int cpu_exec(CPUState *cpu)
348{
349 CPUClass *cc = CPU_GET_CLASS(cpu);
350#ifdef TARGET_I386
351 X86CPU *x86_cpu = X86_CPU(cpu);
352 CPUArchState *env = &x86_cpu->env;
353#endif
354 int ret, interrupt_request;
355 TranslationBlock *tb;
356 uintptr_t next_tb;
357 SyncClocks sc;
358
359
360 current_cpu = cpu;
361
362 if (cpu->halted) {
363#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
364 if ((cpu->interrupt_request & CPU_INTERRUPT_POLL)
365 && replay_interrupt()) {
366 apic_poll_irq(x86_cpu->apic_state);
367 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
368 }
369#endif
370 if (!cpu_has_work(cpu)) {
371 current_cpu = NULL;
372 return EXCP_HALTED;
373 }
374
375 cpu->halted = 0;
376 }
377
378 atomic_mb_set(&tcg_current_cpu, cpu);
379 rcu_read_lock();
380
381 if (unlikely(atomic_mb_read(&exit_request))) {
382 cpu->exit_request = 1;
383 }
384
385 cc->cpu_exec_enter(cpu);
386
387
388
389
390
391
392 init_delay_params(&sc, cpu);
393
394
395 for(;;) {
396 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
397
398 if (cpu->exception_index >= 0) {
399 if (cpu->exception_index >= EXCP_INTERRUPT) {
400
401 ret = cpu->exception_index;
402 if (ret == EXCP_DEBUG) {
403 cpu_handle_debug_exception(cpu);
404 }
405 cpu->exception_index = -1;
406 break;
407 } else {
408#if defined(CONFIG_USER_ONLY)
409
410
411
412#if defined(TARGET_I386)
413 cc->do_interrupt(cpu);
414#endif
415 ret = cpu->exception_index;
416 cpu->exception_index = -1;
417 break;
418#else
419 if (replay_exception()) {
420 cc->do_interrupt(cpu);
421 cpu->exception_index = -1;
422 } else if (!replay_has_interrupt()) {
423
424 ret = EXCP_INTERRUPT;
425 break;
426 }
427#endif
428 }
429 } else if (replay_has_exception()
430 && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
431
432 cpu_exec_nocache(cpu, 1, tb_find_fast(cpu), true);
433 ret = -1;
434 break;
435 }
436
437 next_tb = 0;
438 for(;;) {
439 interrupt_request = cpu->interrupt_request;
440 if (unlikely(interrupt_request)) {
441 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
442
443 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
444 }
445 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
446 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
447 cpu->exception_index = EXCP_DEBUG;
448 cpu_loop_exit(cpu);
449 }
450 if (replay_mode == REPLAY_MODE_PLAY
451 && !replay_has_interrupt()) {
452
453 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
454 replay_interrupt();
455 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
456 cpu->halted = 1;
457 cpu->exception_index = EXCP_HLT;
458 cpu_loop_exit(cpu);
459 }
460#if defined(TARGET_I386)
461 else if (interrupt_request & CPU_INTERRUPT_INIT) {
462 replay_interrupt();
463 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
464 do_cpu_init(x86_cpu);
465 cpu->exception_index = EXCP_HALTED;
466 cpu_loop_exit(cpu);
467 }
468#else
469 else if (interrupt_request & CPU_INTERRUPT_RESET) {
470 replay_interrupt();
471 cpu_reset(cpu);
472 cpu_loop_exit(cpu);
473 }
474#endif
475
476
477
478
479 else {
480 replay_interrupt();
481 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
482 next_tb = 0;
483 }
484 }
485
486
487 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
488 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
489
490
491 next_tb = 0;
492 }
493 }
494 if (unlikely(cpu->exit_request
495 || replay_has_interrupt())) {
496 cpu->exit_request = 0;
497 cpu->exception_index = EXCP_INTERRUPT;
498 cpu_loop_exit(cpu);
499 }
500 tb_lock();
501 tb = tb_find_fast(cpu);
502
503
504 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
505
506
507
508 next_tb = 0;
509 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
510 }
511
512
513
514 if (next_tb != 0 && tb->page_addr[1] == -1
515 && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
516 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
517 next_tb & TB_EXIT_MASK, tb);
518 }
519 tb_unlock();
520 if (likely(!cpu->exit_request)) {
521 trace_exec_tb(tb, tb->pc);
522
523 cpu->current_tb = tb;
524 next_tb = cpu_tb_exec(cpu, tb);
525 cpu->current_tb = NULL;
526 switch (next_tb & TB_EXIT_MASK) {
527 case TB_EXIT_REQUESTED:
528
529
530
531
532
533
534
535
536
537
538 smp_rmb();
539 next_tb = 0;
540 break;
541 case TB_EXIT_ICOUNT_EXPIRED:
542 {
543
544 int insns_left = cpu->icount_decr.u32;
545 if (cpu->icount_extra && insns_left >= 0) {
546
547 cpu->icount_extra += insns_left;
548 insns_left = MIN(0xffff, cpu->icount_extra);
549 cpu->icount_extra -= insns_left;
550 cpu->icount_decr.u16.low = insns_left;
551 } else {
552 if (insns_left > 0) {
553
554 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
555 cpu_exec_nocache(cpu, insns_left, tb, false);
556 align_clocks(&sc, cpu);
557 }
558 cpu->exception_index = EXCP_INTERRUPT;
559 next_tb = 0;
560 cpu_loop_exit(cpu);
561 }
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569
570 align_clocks(&sc, cpu);
571
572
573 }
574 } else {
575#if defined(__clang__) || !QEMU_GNUC_PREREQ(4, 6)
576
577
578
579
580 cpu = current_cpu;
581 cc = CPU_GET_CLASS(cpu);
582#ifdef TARGET_I386
583 x86_cpu = X86_CPU(cpu);
584 env = &x86_cpu->env;
585#endif
586#else
587
588 g_assert(cpu == current_cpu);
589 g_assert(cc == CPU_GET_CLASS(cpu));
590#ifdef TARGET_I386
591 g_assert(x86_cpu == X86_CPU(cpu));
592 g_assert(env == &x86_cpu->env);
593#endif
594#endif
595 cpu->can_do_io = 1;
596 tb_lock_reset();
597 }
598 }
599
600 cc->cpu_exec_exit(cpu);
601 rcu_read_unlock();
602
603
604 current_cpu = NULL;
605
606
607 atomic_set(&tcg_current_cpu, NULL);
608 return ret;
609}
610